1. Field of the Invention
The present invention relates to circuitry implemented in complementary transistor technology that is compatible with multiple voltages.
2. Related Art
Recent half-micron VLSI (Very Large Scale Integration) circuits include CMOS (Complementary Metal Oxide Semiconductor) transistors having gate oxides of approximately 90 angstroms. The power supply specification for this technology is 3.3 volts (plus or minus 10%). The CMOS transistors in such half-micron VLSI circuits may be damaged if their respective gate oxides are subjected to voltages greater than 3.3 volts.
However, 3.3 volt power supplies are not universal. In fact, many older systems use 5 volt power supplies.
Often, it is necessary for a 3.3 volt circuit to communicate with a 5 volt circuit. In such cases, there is a potential for degraded reliability and damage to the CMOS transistors contained in the 3.3 volt circuit.
Three different types of circuit-to-circuit communication are possible. In the first case, a 3.3 volt output drives a nominally 5 volt input. There are usually no reliability problems with this first case.
In the second case, a 5 volt output drives a nominally 3.3 volt input. This second case represents a potential reliability problem, since the CMOS transistors in the 3.3 volt circuit may be damaged if their gate oxides are exposed to voltages over 3.3 volts. A solution to this problem is presented in U.S. Pat. No. 4,704,547 to Kirsch (hereinafter Kirsch). For convenience of reference, FIG. 2 of Kirsch has been substantially reproduced herein as FIG. 1.
Before considering the circuit shown in FIG. 1, it will be useful to consider FIGS. 4A-4H, which illustrate the symbols used herein to represent transistors. The symbols in FIGS. 4A and 4B both represent a normal n-type MOSFET (Metal Oxide Silicon Field Effect Transistor) transistor. A "normal" transistor is defined herein as comprising those transistors normally employed to implement standard digital electronic circuits, such as enhancement mode transistors that are normally off with zero bias applied to their respective gate electrodes. More particularly, "normal" transistors as defined herein represent enhancement mode transistors having the same threshold voltages as the transistors normally used in digital CMOS circuits. Note that the transistor in FIG. 4B is explicitly shown as having a back gate.
The symbols in FIGS. 4C-4E all represent a normal p-type MOSFET transistor. Note that the transistors in FIGS. 4D and 4E are explicitly shown as having back gates.
The symbols in FIGS. 4F-4H all represent unusual, or abnormal, MOSFET transistors. The transistors shown in FIGS. 4F-4H are not normally employed to implement standard digital electronic circuits.
FIGS. 4F and 4G depict intrinsic p-type and intrinsic n-type MOSFET transistors, respectively. An intrinsic p-type MOSFET transistor is an abnormally high threshold p channel device. An intrinsic n-type MOSFET transistor is an abnormally low threshold n channel device.
FIG. 4H depicts a depletion p-type MOSFET transistor. Depletion type transistors are well known. As will be appreciated, the production of depletion type transistors includes an additional mask processing step to apply a channel dopant which is not required in the production of normal transistors. Thus, depletion type transistors are more complicated and more expensive to produce than normal transistors.
Referring now to FIG. 1, an inverter 102 is shown, which includes a protective transistor T22 having a source-drain path that is serially inserted in the path between the drains of logic transistors T21 and T23. Note that complementary transistors T21, T23 otherwise form by themselves a conventional complementary pair. An input logic signal V.sub.IN is applied from a common input node 24 to the gates of transistor T21 and T23, whereas an output logic signal V.sub.OUT is taken from the drain of p-channel transistor T21 and the drain of n-channel transistor T22, at common output node 25.
For typical MOS devices, the n-channel transistors are degraded more rapidly by excessive fields than are p-channel transistors. Hence, protective transistor T22 in the Kirsch patent provides that the source-drain potential of n-channel transistor T23 is limited so as not to exceed a given value, even though the positive power supply potential (+V) increases beyond this value. To achieve this end, the gate voltage of protective transistor T22 is placed at protective voltage V.sub.P with respect to ground. The drain voltage (referenced to ground) on T23 is then limited to V.sub.P -V.sub.th, where V.sub.th is the threshold voltage drop across protective transistor T22. Accordingly, transistor T23 is protected against increases in the positive power supply potential (+V), since the drain voltage of transistor T23 is limited to a transistor threshold voltage drop (typically 0.7 volts to 1.0 volt) below the protective voltage V.sub.P.
The third circuit-to-circuit communication case involves a bidirectional bus, such as in a bidirectional buffer having an input circuit and an output circuit both connected to a pad. This third case represents a potential reliability problem, since the CMOS transistors in the 3.3 volt input and output circuits may be damaged if their gate oxides are exposed to voltages over 3.3 volts (wherein such voltages are applied to the pad).
A solution to this problem is presented in "3.3 V-5 V Compatible I/O Circuit Without Thick Gate Oxide" by Takahashi et al., IEEE 1992 Custom Integrated Circuits Conference, 1992 (hereinafter Takahashi). For convenience of reference, FIG. 1(b) of Takahashi has been substantially reproduced herein as FIG. 2A. FIG. 2B illustrates the symbols used in FIG. 2A to represent different voltage levels.
Referring now to FIG. 2A, an input stage 202 is shown which is protected from voltages applied to a Pad. Specifically, a pull-down transistor MN4 is protected against a high voltage level (that is, greater than 3.3 volts) applied to the Pad by an intrinsic n-type MOSFET transistor MN3. This protection scheme is essentially the same as that described in Kirsch. Specifically, the transistor MN4 is protected since its drain voltage is limited to the gate voltage of the protective transistor MN3 minus the threshold voltage of the protective transistor MN3.
Takahashi also protects a pull-up transistor MP3. Transistor MP2, a depletion P-channel device, is placed between the drain and gate of transistor MP3. When the voltage applied to the Pad goes above VDD (which is typically 3.3 volts), transistor MP2 turns on, so that the voltage across the gate of MP3 is essentially zero.
During normal operation, when MP3 is an active output device, MP2 is ideally always off. This condition is necessary to prevent leakage between node N6 (held low) and the output (held high). However, this condition can only be achieved by tightly controlling the threshold voltage of transistor MP2. In addition, since node N6 cannot go above VDD minus V.sub.tn(MN2), which represents the threshold voltage of transistor MN2, MP3 will leak when it is supposed to be off unless its threshold voltage is always greater than V.sub.tn(MN2).
In order to satisfy these strict threshold voltage requirements, many of the transistors in the Takahashi circuit are implemented as intrinsic devices. For example, transistor MP3 is implemented as an intrinsic p-type transistor, which is an abnormally high threshold p channel device (as discussed above). As shown in FIG. 2A, transistors MN2, MN3, and MN6 are also implemented as intrinsic devices in order to satisfy the threshold voltage requirements discussed above.
Thus, Takahashi solves the problems associated with the third circuit-to-circuit communication case by using abnormal transistor devices and, in particular, by using intrinsic transistor devices. However, the fabrication process involved in producing a circuit which includes normal and abnormal transistor devices is much more complex and expensive than the fabrication process involved in producing a circuit which includes only normal transistor devices. This is the case, since the inclusion of abnormal transistor devices in a circuit introduces additional processing variables (associated with the abnormal transistor devices) which must be considered both independent of and in combination with the processing variables associated with the normal transistor devices.
Additionally, the use of abnormal transistor devices does not solve the problems associated with transistor MP2. As will be appreciated, the threshold voltage of MP2 must be strictly controlled to ensure that MP2 is always off during normal operation. Typical digital fabrication systems, however, have process variances of plus or minus 100 millivolts. Thus, typical digital fabrication systems cannot be used to produce the Takahashi buffer.
Thus, while it may protect transistor devices from the application of high voltages, Takahashi does not represent an ideal solution.